VIA Technologies KT880 Specifications Page 113
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VT8237R Data Sheet
Revision 2.06 December 15, 2004 -105- Device 17 Function 0 Bus Control Registers
Offset 5A – DMA Bandwidth Control (00h)...................RW
7 DMA Channel 7 Bandwidth
0 Normal ...................................................default
1 Improved
6 DMA Channel 6 Bandwidth
0 Normal ...................................................default
1 Improved
5 DMA Channel 5 Bandwidth
0 Normal ...................................................default
1 Improved
4 DMA Single Transfer Mode Bandwidth
0 Normal ...................................................default
1 Improved
3 DMA Channel 3 Bandwidth
0 Normal ...................................................default
1 Improved
2 DMA Channel 2 Bandwidth
0 Normal ...................................................default
1 Improved
1 DMA Channel 1 Bandwidth
0 Normal ...................................................default
1 Improved
0 DMA Channel 0 Bandwidth
0 Normal ...................................................default
1 Improved
The above bits determine if DMA bandwidth is improved for
the specified channel. If enabled, bandwidth improvement is
accomplished by reducing the transaction latency between the
DMA Controller and the LPC Bus Controller.
Offset 5B – Miscellaneous Control 2 (01h) ..................... RW
7-6 Reserved ........................................always reads 0
5 PCI/DMA Memory Cycles Output to PCI Bus
0 Disable................................................... default
1 Enable
4 LPC PCS2
0 Disable................................................... default
1 Enable
3 Bypass APIC De-Assert Message
0 Disable................................................... default
1 Enable
2 APIC HyperTransport Mode
0 Disable................................................... default
1 Enable
1 INTE#, INTF#, INTG#, INTH# (pins GPIO12-15)
0 Disable (GPIO)...................................... default
1 Enable (INT)
0 Dynamic Clock Stop
0 Disable
1 Enable................................................... default
- Data Sheet 1
- Copyright Notice: 2
- Disclaimer Notice: 2
- Offices: 2
- REVISION HISTORY 3
- TABLE OF CONTENTS 4
- LIST OF FIGURES 7
- LIST OF TABLES 8
- VT8237R Data Sheet 10
- OVERVIEW 12
- PIN DESCRIPTIONS 18
- CPU Interface 19
- CPU Speed Control Interface 19
- PCI Bus Interface 20
- Serial EEPROM Interface 21
- Serial ATA Interface 24
- AC97 Audio / Modem Interface 25
- Serial IRQ 25
- PC / PCI DMA 25
- Internal Keyboard Controller 26
- Speaker 26
- Programmable Chip Selects 27
- General Purpose Inputs 27
- General Purpose Outputs 28
- General Purpose I/O 28
- Power and Ground 30
- Strap Pins 31
- REGISTERS 32
- Reserved Default Acc 34
- KB / Mouse Wakeu 34
- APIC Registers Default Acc 34
- SATA Confi 35
- IDE I/O Registers Default Acc 37
- USB Control Default Acc 38
- USB I/O Re 38
- USB Control Default Acc 42
- Host Controller O 42
- AC97 SGD I/O Re 48
- MC97 SGD I/O Re 48
- Power Management Default Acc 49
- Power Management Default Acc 50
- Register Descriptions 51
- .................. RW 58
- ................... RW 58
- ........................RW 63
- ................... RW 64
- Request (00h)...RW 66
- SATA LITE Control (00h) .. RW 66
- .......................RW 73
- ...................... RW 73
- ..................... RW 73
- .......RW 74
- ....................RW 75
- Access Data (00000000h) .RW 99
- ...............RW 101
- ).........................RW 109
- ...... default 110
- ......................RW 112
- ...................RW 113
- ) ..................... RW 113
- .............. RW 123
- 3h (command match) 137
- DataType / SampleRateRW 144
- ....................RWC 145
- Current Count.. RO 146
- 0 SGD Stop Index ... RW 148
- 1 SGD Stop Index ... RW 150
- ................. RW 157
- .... RO 163
- ............ RO 163
- FUNCTIONAL DESCRIPTIONS 172
- ELECTRICAL SPECIFICATIONS 177
- Register Description 178
- Power Requirements 179
- VT8237R 180
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