VIA Technologies EPIA-CL Specifications

Data Sheet CN333 North Bridge with Integrated UniChrome Pro 3D / 2D Graphics Controller Revision 1.0 January 5, 2005 VIA TECHNOLOGIES,

CN333 Data Sheet Revision 1.0, January 5, 2005 -4- Product Features • Extensive Display Support for External Video Output – CRT display interface

CN333 Data Sheet Revision 1.0, January 5, 2005 -5- Overview CN333 SYSTEM OVERVIEW The CN333 is a high performance, cost-effective and energy efficie

CN333 Data Sheet Revision 1.0, January 5, 2005 -6- Overview Ultra V-Link The CN333 North Bridge interfaces to the South Bridge through a high speed

CN333 Data Sheet Revision 1.0, January 5, 2005 -7- Overview 24-Bit FPDplus 12-Bit DVP66 MHz PCI Host Bus InterfaceMe m ory I nt e rface UnitVGA G

CN333 Data Sheet Revision 1.0, January 5, 2005 -8- Overview Desktop Modes for Single Display CRT Maximum Refresh Resolution BPP 60 75 85 100

CN333 Data Sheet Revision 1.0, January 5, 2005 -9- Pin Diagrams PINOUTS Pin Diagrams Figure 3. Ball Diagram (Top View) – Flat Panel / Digital Video

CN333 Data Sheet Revision 1.0, January 5, 2005 -10- Pin Lists Pin Lists Table 2. Pin List (Listed by Pin Number) Pin # Pin Name Pin # Pin Na

CN333 Data Sheet Revision 1.0, January 5, 2005 -11- Pin Lists Table 3. Pin List (Listed by Pin Name) Pin # Pin Name Pin # Pin Name Pin #

CN333 Data Sheet Revision 1.0, January 5, 2005 -12- Pin Lists Table 4. Power, Ground and Voltage Reference Pin List Outer Ring Pins (Intermixed wit

CN333 Data Sheet Revision 1.0, January 5, 2005 -13- Pin Descriptions Pin Descriptions CPU Interface Pin Descriptions CPU Interface Signal Name Pin

Copyright Notice: Copyright © 2004-2005, VIA Technologies Incorporated. All Rights Reserved. No part of this document may be reproduced, transmitte

CN333 Data Sheet Revision 1.0, January 5, 2005 -14- Pin Descriptions The pinouts were defined assuming the ATX PCB layout model shown below (and gen

CN333 Data Sheet Revision 1.0, January 5, 2005 -15- Pin Descriptions Ultra V-Link Pin Descriptions Ultra V-Link Interface Signal Name Pin # I/O S

CN333 Data Sheet Revision 1.0, January 5, 2005 -16- Pin Descriptions CRT and Serial Bus Pin Descriptions CRT Interface Signal Name Pin # I/O Sign

CN333 Data Sheet Revision 1.0, January 5, 2005 -17- Pin Descriptions Flat Panel Display Port (FPDP) Pin Descriptions The FPDP can be configured as e

CN333 Data Sheet Revision 1.0, January 5, 2005 -18- Pin Descriptions Digital Video Port 1 (GDVP1) Pin Descriptions GDVP1 can be configured as either

CN333 Data Sheet Revision 1.0, January 5, 2005 -19- Pin Descriptions Clock, Reset, Power Control, GPIO, Interrupt and Test Pin Descriptions Clocks,

CN333 Data Sheet Revision 1.0, January 5, 2005 -20- Pin Descriptions Compensation and Reference Voltage Pin Descriptions Compensation Signal Name P

CN333 Data Sheet Revision 1.0, January 5, 2005 -21- Pin Descriptions Power Pin Descriptions Analog Power / Ground Signal Name Pin # I/O Signal De

CN333 Data Sheet Revision 1.0, January 5, 2005 -22- Pin Descriptions Strap Pin Descriptions Strap Pins (External pullup / pulldown straps are requir

CN333 Data Sheet Revision 1.0, January 5, 2005 -23- Register Summary Tables REGISTERS Register Overview The following tables summarize the configur

CN333 Data Sheet Revision 1.0, January 5, 2005 -i- Revision History REVISION HISTORY Document Release Date Revision Initials1.0 1/5/05 Initial

CN333 Data Sheet Revision 1.0, January 5, 2005 -24- Register Summary Tables Device 0 Function 0 Registers – AGP Header Registers Offset Configurat

CN333 Data Sheet Revision 1.0, January 5, 2005 -25- Register Summary Tables Device 0 Function 2 Registers – Host CPU Header Registers Offset Confi

CN333 Data Sheet Revision 1.0, January 5, 2005 -26- Register Summary Tables Device 0 Function 3 Registers – DRAM Header Registers Offset Configura

CN333 Data Sheet Revision 1.0, January 5, 2005 -27- Register Summary Tables Function 3 DRAM Device-Specific Registers (continued) Offset Graphics

CN333 Data Sheet Revision 1.0, January 5, 2005 -28- Register Summary Tables Device 0 Function 7 Registers – V-Link / PCI Header Registers Offset C

CN333 Data Sheet Revision 1.0, January 5, 2005 -29- Register Summary Tables Device 1 Registers - PCI-to-PCI Bridge Header Registers Offset Configu

CN333 Data Sheet Revision 1.0, January 5, 2005 -30- Miscellaneous I/O and Configuration Space I/O Miscellaneous I/O One I/O port is defined: Port 2

CN333 Data Sheet Revision 1.0, January 5, 2005 -31- Device 0 Function 0 Register Descriptions - AGP Device 0 Function 0 Registers – AGP Device 0 Fu

CN333 Data Sheet Revision 1.0, January 5, 2005 -32- Device 0 Function 0 Register Descriptions - AGP Device 0 Function 0 Header Registers (continued

CN333 Data Sheet Revision 1.0, January 5, 2005 -33- Device 0 Function 0 Register Descriptions - AGP AGP Miscellaneous Control Offset 4F – Multiple

CN333 Data Sheet Revision 1.0, January 5, 2005 -ii- Table of Contents TABLE OF CONTENTS REVISION HISTORY ...

CN333 Data Sheet Revision 1.0, January 5, 2005 -34- Device 0 Function 0 Register Descriptions - AGP AGP GART / Graphics Aperture The function of th

CN333 Data Sheet Revision 1.0, January 5, 2005 -35- Device 0 Function 1 Register Descriptions – Error Reporting Device 0 Function 1 Registers – Err

CN333 Data Sheet Revision 1.0, January 5, 2005 -36- Device 0 Function 1 Register Descriptions – Error Reporting Device 0 Function 1 Device-Specific

CN333 Data Sheet Revision 1.0, January 5, 2005 -37- Device 0 Function 2 Register Descriptions – Host CPU Device 0 Function 2 Registers – Host CPU D

CN333 Data Sheet Revision 1.0, January 5, 2005 -38- Device 0 Function 2 Register Descriptions – Host CPU Device 0 Function 2 Device-Specific Regist

CN333 Data Sheet Revision 1.0, January 5, 2005 -39- Device 0 Function 2 Register Descriptions – Host CPU Offset 54 – CPU Frequency (00h) ...

CN333 Data Sheet Revision 1.0, January 5, 2005 -40- Device 0 Function 2 Register Descriptions – Host CPU Offset 59 – IPI Control (00h)...

CN333 Data Sheet Revision 1.0, January 5, 2005 -41- Device 0 Function 2 Register Descriptions – Host CPU Offset 60 – DRDY L Timing Control 1 (00h).

CN333 Data Sheet Revision 1.0, January 5, 2005 -42- Device 0 Function 2 Register Descriptions – Host CPU Host CPU AGTL+ I/O Control Offset 70 – Hos

CN333 Data Sheet Revision 1.0, January 5, 2005 -43- Device 0 Function 3 Register Descriptions - DRAM Device 0 Function 3 Registers – DRAM Device 0

CN333 Data Sheet Revision 1.0, January 5, 2005 -iii- Table of Contents DEVICE 0 FUNCTION 2 REGISTERS – HOST CPU...

CN333 Data Sheet Revision 1.0, January 5, 2005 -44- Device 0 Function 3 Register Descriptions - DRAM Device 0 Function 3 Device-Specific Registers

CN333 Data Sheet Revision 1.0, January 5, 2005 -45- Device 0 Function 3 Register Descriptions - DRAM Offset 51-50 - DRAM MA Map Type (2222h) ...

CN333 Data Sheet Revision 1.0, January 5, 2005 -46- Device 0 Function 3 Register Descriptions - DRAM Offset 60 – DRAM Control (00h)...

CN333 Data Sheet Revision 1.0, January 5, 2005 -47- Device 0 Function 3 Register Descriptions - DRAM Offset 69 – DRAM Page Policy Control (00h) ...

CN333 Data Sheet Revision 1.0, January 5, 2005 -48- Device 0 Function 3 Register Descriptions - DRAM Offset 6C – DRAM Clock Control (00h)...

CN333 Data Sheet Revision 1.0, January 5, 2005 -49- Device 0 Function 3 Register Descriptions - DRAM Offset 70 – DRAM DDR Control 1 (00h) ...

CN333 Data Sheet Revision 1.0, January 5, 2005 -50- Device 0 Function 3 Register Descriptions - DRAM Offset 7A – DRAM DQS Capture Ctrl Chan A (44h)

CN333 Data Sheet Revision 1.0, January 5, 2005 -51- Device 0 Function 3 Register Descriptions - DRAM Table 9. 1x Bandwidth (64-Bit DDR) Memory Ad

CN333 Data Sheet Revision 1.0, January 5, 2005 -52- Device 0 Function 3 Register Descriptions - DRAM ROM Shadow Control Offset 80 – C-ROM Shadow Co

CN333 Data Sheet Revision 1.0, January 5, 2005 -53- Device 0 Function 3 Register Descriptions - DRAM DRAM Above 4G Control Offset 84 – Low Top Addr

CN333 Data Sheet Revision 1.0, January 5, 2005 -iv- Lists of Figures and Tables LIST OF FIGURES FIGURE 1. SYSTEM BLOCK DIAGRAM...

CN333 Data Sheet Revision 1.0, January 5, 2005 -54- Device 0 Function 3 Register Descriptions - DRAM UMA Control Offset A0 – CPU Direct Access FB B

CN333 Data Sheet Revision 1.0, January 5, 2005 -55- Device 0 Function 3 Register Descriptions - DRAM Graphics Control Offset B0 – Graphics Control

CN333 Data Sheet Revision 1.0, January 5, 2005 -56- Device 0 Function 3 Register Descriptions - DRAM DRAM Drive Control Offset E0 – DRAM DQSA Drive

CN333 Data Sheet Revision 1.0, January 5, 2005 -57- Device 0 Function 4 Register Descriptions – Power Management Device 0 Function 4 Registers – Po

CN333 Data Sheet Revision 1.0, January 5, 2005 -58- Device 0 Function 4 Register Descriptions – Power Management Device 0 Function 4 Device-Specifi

CN333 Data Sheet Revision 1.0, January 5, 2005 -59- Device 0 Function 7 Register Descriptions – V-Link Device 0 Function 7 Registers – V-Link Devic

CN333 Data Sheet Revision 1.0, January 5, 2005 -60- Device 0 Function 7 Register Descriptions – V-Link Device 0 Function 7 Device-Specific Register

CN333 Data Sheet Revision 1.0, January 5, 2005 -61- Device 0 Function 7 Register Descriptions – V-Link Offset 46 – NB V-Link Misc Control (00h) ...

CN333 Data Sheet Revision 1.0, January 5, 2005 -62- Device 0 Function 7 Register Descriptions – V-Link Offset 4A – SB Downlink Status (88h) ...

CN333 Data Sheet Revision 1.0, January 5, 2005 -63- Device 0 Function 7 Register Descriptions – V-Link PCI Bus Control These registers are normally

CN333 Data Sheet Revision 1.0, January 5, 2005 -1- Product Features CN333 NORTH BRIDGE 133 / 100 MHz VIA C3 Front Side Bus Integrated UniChrome Pro

CN333 Data Sheet Revision 1.0, January 5, 2005 -64- Device 0 Function 7 Register Descriptions – V-Link Offset 75 - PCI Arbitration 1 (00h)...

CN333 Data Sheet Revision 1.0, January 5, 2005 -65- Device 0 Function 7 Register Descriptions – V-Link Graphics Aperture Control Offset 85-84 – Gra

CN333 Data Sheet Revision 1.0, January 5, 2005 -66- Device 0 Function 7 Register Descriptions – V-Link V-Link Compensation / Drive Control Offset B

CN333 Data Sheet Revision 1.0, January 5, 2005 -67- Device 1 Register Descriptions - PCI-to-PCI Bridge Device 1 Registers – PCI-to-PCI Bridge Devic

CN333 Data Sheet Revision 1.0, January 5, 2005 -68- Device 1 Register Descriptions - PCI-to-PCI Bridge Device 1 Offset 13-10 – Graphics Aperture Ba

CN333 Data Sheet Revision 1.0, January 5, 2005 -69- Device 1 Register Descriptions - PCI-to-PCI Bridge Device 1 Device-Specific Registers AGP Bus C

CN333 Data Sheet Revision 1.0, January 5, 2005 -70- Device 1 Register Descriptions - PCI-to-PCI Bridge Device 1 Offset 43 - AGP Master Latency Tim

CN333 Data Sheet Revision 1.0, January 5, 2005 -71- Electrical Specifications ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Table 11. Absolute

CN333 Data Sheet Revision 1.0, January 5, 2005 -72- Mechanical Specifications MECHANICAL SPECIFICATIONS Figure 5. Mechanical Specifications – 681-

CN333 Data Sheet Revision 1.0, January 5, 2005 -73- Mechanical Specifications Figure 6. Lead-Free Mechanical Specifications – 681-Pin HSBGA Ball

CN333 Data Sheet Revision 1.0, January 5, 2005 -2- Product Features • Advanced System Power Management Support – ACPI 2.0 and PCI Bus Power Manage

CN333 Data Sheet Revision 1.0, January 5, 2005 -3- Product Features Video Acceleration High Quality Video Processor – RGB555, RGB565, RGB8888 and Y